Semiconductor chips are vastly complex structures. There are numerous metal lines of miniscule dimension in close proximity to one another. There are diffusions, polysilicon shapes, and insulator layers, all of which need to be fabricated to exacting tolerances. An error in any step of fabrication or the presence of even the smallest defect can cause a failure in the operation of a chip. Failures on semiconductor chips may be the result of random defects or systematic defects on the chips. Design problems with semiconductor devices are traditionally overcome by having layout design rule checks (DRCs) evaluated against a chip layout prior to beginning mask and chip fabrication. With the advent of deep sub-micron technologies, new fault models are being detected which cannot be covered by traditional design rule checking processes.
There remains a need for an improved failure analysis process.